System control and clock distribution – Architecture and technical overview

2.9 System control and clock distribution

Power E1080 server requires UPIC, FSP & SMP cables for inter-drawer connections:

Ê UPIC cables allow the system nodes to power the System Control Unit (SCU)

Ê FSP cables are required to provide system control to the components

Ê SMP cables are necessary to extend the A bus interface that connect the Power10 processors together across the system nodes

Similar to the previous generation of Power System E980 server, two service processors are available for redundancy. They are hosted in the SCU and communicates with the system nodes by using the FSI/PSI bus connectors that are at the rear of the SCU and the system nodes.

All of the service processor communication between the control unit and the system nodes flows though the service processor cables. In comparison to previous generations, the Power E1080 associated SCU is no longer hosting the system clock. Each system node hosts its own redundant clocks.

The cables that are required for communications between the SCU and system nodes depend on the number of system nodes that are installed. When a system node is added, a new set of cables must be also added.

The cables that are necessary for each system node are grouped under a single feature code, which allows for an easier configuration. Each cable set includes a pair of FSP cables, and when applicable SMP cables and Universal Power Interconnect Cables (UPIC) cables.

Table 2-28 lists the available feature codes.

Table 2-28 Features for cable sets

Initial orders of Power E1080 server includes one #EFCH, which is required to connect the system node with System Control Unit (SCU). This configuration does not require SMP cables, which are necessary only for configurations with two or more system nodes.

Cable sets feature codes are incremental and depend on the number of installed system nodes:

Ê One system node: #EFCH

Ê Two system nodes: #EFCH and #EFCE

Ê Three system nodes: #EFCH, #EFCE, and #EFCF

Ê Four system nodes: #EFCH, #EFCE, #EFCF, and #EFCG

The redundant Flexible Service Processor (FSP) provides proprietary interface communication, such as FRU Service Interface (FSI) and Processor Support Interface (PSI) to the system nodes.

Chapter 2. Architecture and technical overview               109

PSI is used for FSP-host processor unit communication. PSI is a clock synchronous bidirectional interface for control communication. Each FSP in the SCU has four PSI interfaces and are connected such that whichever FSP becomes Primary can control the entire system.

FSI in the Power E1080 server is a serial point-to-point connection used for device communication in the overall System Control Structure design.

The FSI connection network is across FSP to FSP connections inside the SCU, FSP to system node through clocking and control logic. They connect FSPs in the SCU to system node elements and the Power10 to Power10 processor chips on the system node planar inside the system node. Similar to PSI network, whichever FSP becomes Primary can control the entire server.

Figure 2-32 shows UPIC and FSP cabling between a single system node and SCU.

Figure 2-32 UPIC & FSP connection between SCU and single System Node

110      IBM Power E1080: Technical Overview and Introduction

Figure 2-33 shows UPIC & FSP cabling between two system nodes and SCU.

Figure 2-33 UPIC & FSP connection between SCU and two System Nodes

In a single system node configuration, two UPIC cables connect to the SCU and provide redundant power source from the system node. The SCU power source for two or more system nodes is supplied by the first and second system node. When Power E1080 supports more than two system nodes, power output ports on the third and forth system node are not used.

The system reference clock source is responsible for providing a synchronized clock signal to all functional units. Each system node of a Power E1080 server uses its own private set of two redundant system clock or control cards. If a failure occurs in any of the clock or control cards, the second card ensures continued operation of the system until a replacement is scheduled. Similar to Power E980, Power E1080 server does not require a global reference clock source in the system control.

Chapter 2. Architecture and technical overview               111

Figure 2-34 shows UPIC and FSP cabling between three system nodes and SCU.

Figure 2-34 UPIC and FSP connection between SCU and three system nodes

112      IBM Power E1080: Technical Overview and Introduction

Figure 2-35 shows UPIC and FSP cabling between four system nodes and SCU.

Figure 2-35 UPIC and FSP connection between SCU and four system nodes

Chapter 2. Architecture and technical overview                       113